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LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ ZERO DELAY BUFFER
ICS87973I-147
General Description
ICS
HiPerClockSTM
Features
* * * * * * * * * * * * *
Fully integrated PLL Fourteen LVCMOS/LVTTL outputs to include: twelve clocks, one feedback, one sync Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL reference clock inputs CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL Output frequency range: 10MHz to 150MHz VCO range: 240MHz to 500MHz Output skew: 200ps (maximum) Cycle-to-cycle jitter, (all banks /4): 55ps (maximum) Full 3.3V supply voltage -40C to 85C ambient operating temperature Compatible with PowerPCTM and PentiumTM Microprocessors Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
The ICS87973I-147 is a LVCMOS/LVTTL clock generator and a member of the HiPerClockSTM family of High Performance Clock Solutions from IDT. The ICS87973I-147 has three selectable inputs and provides 14 LVCMOS/LVTTL outputs.
The ICS87973I-147 is a highly flexible device. The three selectable inputs (1 differential and 2 single ended inputs) are often used in systems requiring redundant clock sources. Up to three different output frequencies can be generated among the three output banks. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 10MHz to 150MHz. The input frequency range is 6MHz to 120MHz. The ICS87973I-147 also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. Example Applications: 1.System Clock generator: Use a 16.66MHz reference clock to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. 2.Line Card Multiplier: Multiply differential 62.5MHz from a back plane to single-ended 125MHz for the line Card ASICs and Gigabit Ethernet Serdes. 3.Zero Delay buffer for Synchronous memory: Fanout up to twelve 100MHz copies from a memory controller reference clock to the memory chips on a memory module with zero delay.
Pin Assignment
GNDO QB0 VDDO QB1 GNDO QB2 VDDO QB3 EXT_FB GNDO QFB VDD FSEL_FB0
39 38 37 36 35 34 33 32 31 30 29 28 27 FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VDDO QA2 GNDO QA1 VDDO QA0 GNDO VCO_SEL 40 41 42 43 44 45 46 47 48 49 50 51 52 1
GNDI
26 25 24 23 22 21 20 19 18 17 16 15 14 2 3 4 5 6 7 8 9 10 11 12 13
FRZ_DATA FSEL_FB2 PLL_SEL REF_SEL CLK_SEL CLK0 CLK1 CLK nCLK nMR/OE FRZ_CLK VDDA
FSEL_FB1 QSYNC GNDO QC0 VDDO QC1 FSEL_C0 FSEL_C1 QC2 VDDO QC3 GNDO INV_CLK
ICS87973I-147 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y Package Top View
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Block Diagram
VCO_SEL Pullup PLL_SEL Pullup REF_SEL Pullup CLK Pullup nCLK CLK0 Pullup CLK1 Pullup CLK_SEL Pullup EXT_FB Pullup
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QA0 QA1 QA2 QA3
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QB0 QB1 QB2 QB3
FSEL_FB2
nMR/OE
Pullup
QC0
SYNC FRZ SYNC FRZ SYNC FRZ
QC1 QC2 QC3 QFB
FSEL_A[0:1] Pullup FSEL_B[0:1]
Pullup
2 2 2 3
SYNC FRZ
FSEL_C[0:1] Pullup FSEL_FB[0:2] Pullup
QSYNC
FRZ_CLK Pullup FRZ_DATA Pullup
INV_CLK Pullup
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Simplified Block Diagram
nMR/OE
CLK Pullup nCLK CLK0 Pullup CLK1 Pullup CLK_SEL REF_SEL
Pullup Pullup
1 0 0 1 VCO RANGE 240MHz - 500MHz 0 /2 0 1 /1 1
FSEL_A[0:1]
2
PLL
FSEL_ A1 A0 00 01 10 11
QAx /4 /6 /8 /12
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QA0 QA1 QA2 QA3
EXT_FB Pullup
FSEL_B[0:1]
2
VCO_SEL Pullup PLL_SEL Pullup
FSEL_ B1 B0 00 01 10 11
QBx /4 /6 /8 /10
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QB0 QB1 QB2 QB3
FSEL_C[0:1]
2
FSEL_ C1 C0 00 01 10 11
QCx /2 /4 /6 /8
Pullup
QC0
SYNC FRZ
QC1 QC2 QC3
0
SYNC FRZ SYNC FRZ
1 INV_CLK
3
FSEL_FB[0:2]
FSEL_ FB2 FB1 FB0 QFB 0 0 0 /4 0 0 1 /6 0 1 0 /8 0 1 1 /10 1 0 0 /8 1 0 1 /12 1 1 0 /16 1 1 1 /20
FRZ_CLK Pullup FRZ_DATA Pullup
OUTPUT DISABLE CIRCUITRY SYNC FRZ
QFB
QSYNC
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Table 1. Pin Descriptions
Number 1 2 3 4 5, 26, 27 6 Name GNDI nMR/OE FRZ_CLK FRZ_DATA FSEL_FB2, FSEL_FB1, FSEL_FB0 PLL_SEL Type Power Input Input Input Input Pullup Pullup Pullup Pullup Description Power supply ground. Master reset and output enable. When HIGH, enables the outputs. When LOW, resets the outputs in a high-impedance state and resets output divide circuitry. Enables and disables all outputs. LVCMOS / LVTTL interface levels. Clock input for freeze circuitry. LVCMOS / LVTTL interface levels. Configuration data input for freeze circuitry. LVCMOS / LVTTL interface levels. Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels. See Table 3B. Selects between the PLL and reference clocks as the input to the output dividers. When HIGH, selects PLL. When LOW, bypasses the PLL and reference clocks. LVCMOS / LVTTL interface levels. Selects between CLK0 or CLK1 and CLK, nCLK inputs. When LOW, selects CLK0 or CLK1. When HIGH, CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Clock select input. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. Single-ended reference clock inputs. LVCMOS/LVTTL interface levels. Non-inverting differential clock input. Inverting differential clock input. VDD/2 default when left floating. Analog supply pin. Pullup Inverted clock select for QC2 and QC3 outputs. LVCMOS / LVTTL interface levels. Power supply ground.
Input
Pullup
7 8 9, 10 11 12 13 14 15, 24, 30, 35, 39, 47, 51 16, 18, 21, 23 17, 22, 33, 37, 45, 49 19, 20 25 28 29 31 32, 34, 36, 38 40, 41 42, 43 44, 46 48, 50 52
REF_SEL CLK_SEL CLK0, CLK1 CLK nCLK VDDA INV_CLK GNDO QC3, QC2, QC1, QC0 VDDO FSEL_C1, FSEL_C0 QYSNC VDD QFB EXT_FB QB3, QB2, QB1, QB0 FSEL_B1, FSEL_B0 FSEL_A1, FSEL_A0 QA3, QA2, QA1, QA0 VCO_SEL
Input Input Input Input Input Power Input Power
Pullup Pullup Pullup Pullup
Output Power Input Output Power Output Input Output Input Input Output Input Pullup Pullup Pullup Pullup Pullup
Single-ended Bank C clock outputs. LVCMOS/ LVTTL interface levels. Output power supply pins. Select pins for Bank C outputs. LVCMOS / LVTTL interface levels. See Table 3A. Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing Diagrams. LVCMOS / LVTTL interface levels. Power supply pin. Single-ended feedback clock output. LVCMOS / LVTTL interface levels. External feedback. LVCMOS / LVTTL interface levels. Single-ended Bank B clock outputs. LVCMOS/ LVTTL interface levels. Select pins for Bank B outputs. LVCMOS / LVTTL interface levels. See Table 3A. Select pins for Bank A outputs. LVCMOS / LVTTL interface levels. See Table 3A. Single-ended Bank A clock outputs. LVCMOS/ LVTTL interface levels. Selects VCO. When HIGH, selects VCO / 1. When LOW, selects VCO / 2. LVCMOS / LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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Table 2. Pin Characteristics
Symbol CIN RPULLUP CPD ROUT Parameter Input Capacitance Input Pullup Resistor Power Dissipation Capacitance (per output) Output Impedance VDD, VDDA, VDDO = 3.465V 5 7 Test Conditions Minimum Typical 4 51 18 12 Maximum Units pF k pF
Function Tables
Table 3A. Output Bank Configuration Select Function Table
Inputs FSEL_A1 0 0 1 1 FSEL_A0 0 1 0 1 Outputs QA /4 /6 /8 /12 Inputs FSEL_B1 0 0 1 1 FSEL_B0 0 1 0 1 Outputs QB /4 /6 /8 /10 Inputs FSEL_C1 0 0 1 1 FSEL_C0 0 1 0 1 Outputs QC /2 /4 /6 /8
Table 3B. Feedback Configuration Select Function Table
Inputs FSEL_FB2 0 0 0 0 1 1 1 1 FSEL_FB1 0 0 1 1 0 0 1 1 FSEL_FB0 0 1 0 1 0 1 0 1 Outputs QFB /4 /6 /8 /10 /8 /12 /16 /20
Table 3C. Control Input Select Function Table
Control Pin VCO_SEL REF_SEL CLK_SEL PLL_SEL nMR/OE INV_CLK Logic 0 VCO/2 CLK0 or CLK1 CLK0 BYPASS PLL Master Reset/Output High-Impedance Non-Inverted QC2, QC3 Logic 1 VCO XTAL CLK1 Enable PLL Enable Outputs Inverted QC2, QC3
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fVCO
1:1 Mode
QA QC QSYNC
2:1 Mode
QA QC QSYNC
3:1 Mode
QC(/2) QA(/4) QSYNC
3:2 Mode
QC(/2) QA(/8) QSYNC
4:1 Mode
QC(/2) QA(/8) QSYNC
4:3 Mode
QA(/6) QC(/8) QSYNC
6:1 Mode
QA(/12) QC(/2) QSYNC
Figure 1. Timing Diagrams
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 42.3C/W (0 lfpm) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDA = VDDO = 3.3V 5%, TA = -40C to 85C
Symbol VDD VDDA VDDO IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 225 20 Units V V V mA mA
Table 4B. DC Characteristics, VDD = VDDA = VDDO = 3.3V 5%, TA = -40C to 85C
Symbol VIH VIL IIN VOH VOL VPP VCMRP Parameter Input High Voltage Input Low Voltage Input Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Input Voltage; NOTE 2, 3 Common Mode Input Voltage; NOTE 2, 3 CLK, nCLK CLK, nCLK IOH = -20mA IOL = 20mA 0.3 VDD - 2 2.4 0.5 1 VDD - 0.6 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 120 Units V V A V V V V
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagram. NOTE 2: VIL should not be less than -0.3V. NOTE 3: Common mode input voltage is defined as VIH.
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Table 5. Input Frequency Characteristics, VDD = VDDA = VDDO = 3.3V 5%, TA = -40C to 85C
Symbol FIN Parameter CLK0, CLK1; NOTE 1 Input Frequency FRZ_CLK 20 MHz Test Conditions Minimum Typical Maximum 120 Units MHz
NOTE 1: Input frequency depends on the feedback divide ratio to ensure "clock * feedback divide" is in the VCO range of 240MHz to 500MHz.
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = VDDA = VDDO = 3.3V 5%, TA = -40C to 85C
Symbol Parameter Test Conditions /2 fMAX Output Frequency /4 /6 /8 CLK0 t(O) tsk(o) tjit(cc) fVCO tLOCK tR / tF odc tPZL, tPZH tPLZL, tPHZ Static Phase Offset; NOTE 1 CLK1 CLK, nCLK Output Skew; NOTE 2, 3 Cycle-to-Cycle Jitter; NOTE 3 PLL VCO Lock Range PLL Lock Time; NOTE 4 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 4 Output Disable Time; NOTE 4 0.8V to 2V 150 45 All Banks / 4 240 QFB / 8, In Frequency = 50MHz -10 -65 -130 145 90 18 Minimum Typical Maximum 150 125 83.33 62.5 300 245 165 200 55 500 10 700 55 10 8 Units MHz MHz MHz MHz ps ps ps ps ps MHz ms ps % ns ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
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Parameter Measurement Information
1.65V5%
VDD VDD, VDDA, VDDO
SCOPE
nCLK
Qx
CLK
V
PP
Cross Points
V
CMR
LVCMOS
GND
GND
-1.65V5%
LVCMOS Output Load AC Test Circuit
Differential Input Level
V
QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB
DDO
V
DDO
V
DDO
2 tcycle n
2
2 tcycle n+1
Qx
tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles
Cycle-to-Cycle Jitter
CLK0, CLK1
EXT_FB
t(O)
t(O) mean = Static Phase Offset
Where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges
Where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges
LVCMOS Static Phase Offset
Differential Static Phase Offset
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t(O)

Qy
tsk(o)
Output Skew
VDD 2
nCLK
VDD
nCLK
2
VDD 2
EXT_FB
VDD 2
t(O) mean = Static Phase Offset
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Parameter Measurement Information, continued
V
QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB
DDO
2
t PW
t
PERIOD
QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB
2V 0.8V tR
2V 0.8V tF
odc =
t PW t PERIOD
x 100%
Output Duty Cycle/Pulse Width Period
Output Rise/Fall Time
Application Information
Recommendations for Unused Input and Output Pins Inputs:
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground.
Outputs:
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no trace attached.
CLK Inputs
For applications not requiring the use of the clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK to ground.
LVCMOS Control Pins
All control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
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Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS87973I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
Figure 2. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_BIAS = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_BIAS in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_BIAS should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK
V_Bias nCLK C1 0.1u
R2 1K
Figure 3. Single-Ended Signal Driving Differential Input
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Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 4A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V 1.8V Zo = 50 Zo = 50 CLK Zo = 50 Zo = 50 nCLK nCLK CLK 3.3V
LVPECL HiPerClockS Input
R1 50 R2 50
HiPerClockS Input
LVHSTL IDT HiPerClockS LVHSTL Driver
R1 50 R2 50
R2 50
Figure 4A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver
Figure 4B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
3.3V 3.3V 3.3V R3 125 Zo = 50 CLK CLK Zo = 50 nCLK R1 100 R4 125 3.3V 3.3V Zo = 50
LVPECL
R1 84 R2 84
HiPerClockS Input
Zo = 50
nCLK
LVDS
Receiver
Figure 4C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
Figure 4D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver
2.5V
3.3V
*R3
33
Zo = 50 CLK Zo = 50 nCLK
HCSL
*R4
33 R1 50 R2 50
HiPerClockS Input
*Optional - R3 and R4 can be 0
Figure 4E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver
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Using the Output Freeze Circuitry
OVERVIEW
To enable low power states within a system, each output of ICS87973I-147 (Except QC0 and QFB) can be individually frozen (stopped in the logic "0" state) using a simple serial interface to a 12 bit shift register. A serial interface was chosen to eliminate the need for each output to have its own Output Enable pin, which would dramatically increase pin count and package cost. Common sources in a system that can be used to drive the ICS87973I-147 serial interface are FPGA's and ASICs. each FRZ_DATA bit with the rising edge of the FRZ_CLK signal. To place an output in the freeze state, a logic "0" must be written to the respective freeze enable bit in the shift register. To unfreeze an output, a logic "1" must be written to the respective freeze enable bit. Outputs will not become enabled/disabled until all 12 data bits are shifted into the shift register. When all 12 data bits are shifted in the register, the next rising edge of FRZ_CLK will enable or disable the outputs. If the bit that is following the 12th bit in the register is a logic "0", it is used for the start bit of the next cycle; otherwise, the device will wait and won't start the next cycle until it sees a logic "0" bit. Freezing and unfreezing of the output clock is synchronous (see the timing diagram below). When going into a frozen state, the output clock will go LOW at the time it would normally go LOW, and the freeze logic will keep the output low until unfrozen. Likewise, when coming out of the frozen state, the output will go HIGH only when it would normally go HIGH. This logic, therefore, prevents runt pulses when going into and out of the frozen state.
PROTOCOL
The Serial interface consists of two pins, FRZ_Data (Freeze Data) and FRZ_CLK (Freeze Clock). Each of the outputs which can be frozen has its own freeze enable bit in the 12 bit shift register. The sequence is started by supplying a logic "0" start bit followed by 12NRZ freeze enable bits. The period of each FRZ_DATA bit equals the period of the FRZ_CLK signal. The FRZ_DATA serial transmission should be timed so the ICS87973I-147 can sample
FRZ_DATA
rt Sta it B
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC1
QC2
QC3 QSYNC
FRZ_CLK
Figure 5A. Freeze Data Input Protocol
Qx FREEZE Internal
Qx Internal
Qx Out
Figure 5. Output Disable Timing Diagram
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FRZ Latched
FRZ Clocked
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Schmatic Example
Figure 6 shows a schematic example of using ICS87973I-147. This example shows general design of input, output termination, logic control input pull up/down and power supply filtering. In this example, the clock input is driven by an LVCMOS driver.
R1
43
Zo = 50
VDD
Serial Clcok
R9
1K
R8 1K
VDD
Serial Data
R10
1K
RS
Zo = 50
LVCMOS CLOCK R7 10 - 15 C16 10u R5 1K R6 1K
1 2 3 4 5 6 7 8 9 10 11 12 13
VCO_SEL GNDO QA0 VDDO QA1 GNDO QA2 VDDO QA3 FSEL_A0 FSEL_A1 FSEL_B0 FSEL_B1
VDD
U1
52 51 50 49 48 47 46 45 44 43 42 41 40
GNDI nMR/OE FRZ_CLK FRZ_DATA FSEL_FB2 PLL_SEL REF_SEL CLK_SEL CLK0 CLK1 CLK nCLK VDDA INV_CLK GNDO QC3 VDDO QC2 FSEL_C1 FSEL_C0 QC1 VDDO QC0 GNDO QSYNC FSEL_FB1
GNDO QB0 VDDO QB1 GNDO QB2 VDDO QB3 EXT_FB GNDO QFB VDD FSEL_FB0
39 38 37 36 35 34 33 32 31 30 29 28 27
VDD
14 15 16 17 18 19 20 21 22 23 24 25 26
C11 0.01u
ICS87973I-147
R2
43
Zo = 50
Logic Input Pin Examples
VDD
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 Not Install
R4 1K
R3
43
Zo = 50
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
(U1-17)
VDD
(U1-22)
(U1-28)
(U1-33)
(U1-37)
(U1-45)
(U1-49)
C3 0.1uF
C4 0.1uF
C5 0.1uF
C6 0.1uF
C7 0.1uF
C8 0.1uF
C9 0.1uF
VDD=3.3V
ICS87973I-147 Schematic Layout
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ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Reliability Information
Table 7. JA vs. Air Flow Table for a 52 Lead LQFP
JA by Velocity Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 58.0C/W 42.3C/W 200 47.1C/W 36.4C/W 500 42.0C/W 34.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS87973I-147: 8364 Pin Compatible with MPC973
IDTTM / ICSTM LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
15
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Package Outline and Package Dimensions
Package Outline - Y Suffix for 52 Lead LQFP
Table 8. Package Dimensions for 52 Lead LQFP
JEDEC Variation: BCC All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 52 A 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.22 0.38 c 0.09 0.20 D&E 12.00 Basic D1 & E1 10.00 Basic D2 & E2 7.80 Ref. e 0.65 Basic L 0.45 0.60 0.75 0 7 ccc 0.10 Reference Document: JEDEC Publication 95, MS-026
IDTTM / ICSTM LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
16
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Ordering Information
Table 9. Ordering Information
Part/Order Number 87973DYI-147 87973DYI-147T 87973DYI-147LF 87973DYI-147LFT Marking ICS7973DYI-147 ICS87973DYI-147 ICS87973DI147L ICS87973DI147L Package 52 Lead LQFP 52 Lead LQFP "Lead-Free" 52 Lead LQFP "Lead-Free" 52 Lead LQFP Shipping Packaging Tray 1000 Tape & Reel Tray 1000 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
IDTTM / ICSTM LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
17
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Revision History Sheet
Rev Table T4B T6 A T8 T9 Page 7 8 10 12 16 17 Description of Change Differential DC Characteristics Table - updated NOTES. AC Characteristics Table - added thermal note. Added Recommendations for Unused Input and Output Pins section. Updated Differetnial Clock Input Interface section. UpdatePackage Outline and Package Dimensions Table. Ordering Information Table - added lead-free part number and marking. Date
12/9/08
IDTTM / ICSTM LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
18
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Contact Information:
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Technical Support
netcom@idt.com +480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA)
www.IDT.com
(c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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